1. Field of the Invention
The present invention relates to a digital filter, and particularly to a variable-gain digital filter, which is a crucial technology used for such purposes as restricting bandwidth in the field of digital communication widely employed in mobile communication.
2. Description of the Related Art
In a system in which a number of types of gain are present in the same time slot such as in an IS-95 (Interim Standard 95, a digital portable telephone system mode standard in the U.S.) system, gain regulation (switching) is conventionally carried out in a section preceding the bandwidth restricting (digital) filter. If this restricting is carried out in a succeeding section, discontinuity points occur in the output and the bandwidth restricting characteristic of the filter will no longer be satisfied.
Thus, as shown in FIG. 1, gain selector 51 and multiplier 52 are arranged to precede digital filter 53, and gain that is selected in gain selector 51 for data that have undergone baseband processing is multiplied and the result then applied to digital filter 53. If X bits is the data that have undergone baseband processing and Y bits is the number of bits of gain in this case, the input to digital filter 53 is X+Y bits if computation is carried out without any loss of accuracy, and the construction of digital filter 53 is a circuit such as shown in FIG. 2.
Digital filter 53 shown in FIG. 2 is provided with a selector that switches input data and a coefficient sequence n times (where n is the filter order) in one time slot. Digital filter 53 is a circuit that realizes FIR (Finite Impulse Response) filtering by time division processing. The operation is equivalent to the circuit shown in FIG. 4 that lacks multiplier 16 and selector 15. As shown in the timing chart of FIG. 3, input data IN(N)-IN(N-1) undergo time division multiplexing in selector SEL13, and after being multiplied with time division multiplexed coefficients k1–kn by selector SEL14, the result is integrated. Although the time division process enables the elimination of the multiplier and adder, a number (X+Y)×n bits of flip-flops are required because the number of input bits is X+Y, and this large number of components raises the problem of circuit scale.
In an IS-95 system that employs CDMA (Code Division Multiple Access), symbols having different gain must be transmitted within one frame. If gain is regulated in a section following the bandwidth restricting filter in such a case, discontinuity points will occur in the output and the filter will fail to satisfy the filter bandwidth restriction characteristic as described hereinabove. Gain must therefore be regulated in a section preceding the filter.
As described hereinabove using the prior art example of FIG. 1, selector 51 and multiplier 52 for regulating gain are provided in a section before the filter in the prior art, and if X is the number of bits of data input and Y is the number of bits of gain, the number of bits of input of digital filter 53 will be X+Y bits. Accordingly, a number (X+Y)×n bits of FF (flip-flops) are required in digital filter 53 in the case of the prior-art example.